RFIC Design Engineer Working Student
HFE - RWTH AachenSep 2025 – Present
- Further Work on the Transmitter within an integrated RF Gate-Driver
- Design of a Phased-Locked Loop
- in Cadence Virtuoso using 65 nm low power CMOS technology node
About Me
I am a M.Sc. Electrical Engineering student at RWTH Aachen (major in Telecommunications) with hands-on RFIC design experience in 65 nm CMOS. My academic and project work centers on taking Analog/RF circuits from concept to verified layout.
Work Experience
Working Student
ISEA - RWTH AachenOct 2023 – Jan 2025
- Multiple jobs in the area of Power Electronics including microcontroller programming, student tutoring and design of Matlab-based GUIs
Academic Work
Seminar on Modulation Strategies of Switching Mode Power Amplifiers
HFE - RWTH AachenApril 2026 – Present
- Filler
Laboratory "Analog- & Mixed-Signal-Electronics"
IAS - RWTH AachenOct 2025 – Jan 2026
- Schematic level design and simulation of RF, analog and mixed signal circuits (Op-Amp, VCO, LNA, Mixer, LDO, DC-DC Converter)
- in Cadence Virtuoso using gpdk090, generic 90 nm CMOS technology node
Bachelor's thesis "Design and Layout of a System-Component of the Transmitter within an integrated Radio-Frequency Gate-Driver"
HFE - RWTH AachenApr 2025 – Jul 2025
- Design of a BFSK signal generator at 2.4-2.5GHz
- Implementation of schematic & layout in Cadence Virtuoso
- Simulation and Verification using Spectre, Maestro and Calibre DRC/LVS/PEX
- 65 nm low power CMOS technology node
- Documentation of methodology and results (grade 1.0/1.0)
Institute Project "Design of integrated mixed-signal circuits"
IAS - RWTH AachenApr 2024 – Jul 2024
- Schematic Level design and simulation of basic analog and mixed signal circuits
- Final project: Design of a high gain three-stage operational amplifier
- in Cadence Virtuoso using gpdk090, generic 90 nm CMOS technology node
Technical Skills
Software & Tools
Programming Languages
Languages
Get In Touch
Feel free to reach out!
